XC3S200-5FT256C

Product Summary

The XC3S200-5FT256C is a Field-Programmable Gate Array specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. It offers densities ranging from 50,000 to five million system gates. The XC3S200-5FT256C builds on the success of the earlier Spartan-IIE family by increasing the amount of logic resources, the capacity of internal RAM, the total number of I/Os, and the overall level of performance as well as by improving clock management functions. Numerous enhancements derive from state-of-the-art Virtex-II technology. The XC3S200-5FT256C enhancement, combined with advanced process technology, delivers more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry.

Parametrics

XC3S200-5FT256C absolute maximum ratings: (1)Internal supply voltage: –0.5 to 1.32 V; (2)Auxiliary supply voltage: –0.5 to 3.00 V; (3)Output driver supply voltage: –0.5 to 3.75 V; (4)Input reference voltage: –0.5 to VCCO+0.5 V; (5)Voltage applied to all User I/O pins and Dual-Purpose pins: –0.5 to VCCAUX+0.5 V at Driver in a high-impedance state, –0.5 to VCCO+0.5 V at Voltage applied to all Dedicated pins; (6)Junction temperature: 125 ℃ at VCCO < 3.0V, 105 ℃ at VCCO > 3.0V; (7)Storage temperature: –65 to 150 ℃.

Features

XC3S200-5FT256C features: (1)Very low cost, high-performance logic solution for high-volume, consumer-oriented applications: Densities as high as 74,880 logic cells, Three power rails: for core (1.2V), I/Os (1.2V to 3.3V), and auxiliary purposes (2.5V); (2)SelectIO signaling: Up to 784 I/O pins, 622 Mb/s data transfer rate per I/O, 18 single-ended signal standards, 6 differential I/O standards including LVDS, RSDS, Termination by Digitally Controlled Impedance, Signal swing ranging from 1.14V to 3.45V, Double Data Rate (DDR) support; (3)Logic resources: Abundant logic cells with shift register capability, Wide multiplexers, Fast look-ahead carry logic, Dedicated 18 x 18 multipliers, JTAG logic compatible with IEEE 1149.1/1532.

Diagrams